Modern microprocessors are complex logic circuits that contain many millions of transistors integrated onto a small semiconductor chip. Microprocessors operate in synchronism with a clock signal. They typically include a phase locked loop (PLL) to increase the frequency of an input clock signal to higher operating frequencies. The higher frequency clock signal is distributed to various circuit blocks such as caches, instruction decoders, register files, arithmetic logic units, and the like in a hierarchy known as a “clock tree”. The clock tree has a main trunk from the PLL, major branches that are routed in different directions on the chip, and sub-branches until the clock signals reach the actual circuitry. The clock tree typically re-buffers the clock signals at each branch and sub-branch.
Dynamic power in clocked complementary metal-oxide-semiconductor (CMOS) circuits is a function of the dynamic capacitance and both the frequency of operation and the square of the voltage, according to the formula P=CV2f. The required voltage in turn is related to the frequency of operation; at faster speeds, higher voltages are required for proper operation. Conversely operation at lower speeds reduces power consumption by both reducing the frequency and reducing the required voltage.
Although modern, deep sub-micron CMOS semiconductor manufacturing technologies have allowed microprocessor chips to remain relatively small, the clock signals must be distributed widely around the chip. The signal lines that carry the clock signals have large capacitances because of the distances involved, and therefore they consume a significant portion of the chip's power budget. For example, the clock distribution network may account for about 10% or more of the overall chip power budget.
Because of the high power consumption of the clock tree, some engineers have devised clock trees whose PLLs output the main clock signal at half of the desired operating frequency. The clock tree distributes the half-speed clock signal to save power. Then a set of local clock doublers increase the frequency of the half-speed clock signal at the branches or leaves of the tree back to the desired operating frequency. Unfortunately, known clock doublers have problems themselves, including high power consumption and the inability to provide a symmetrical 50% duty cycle. The drawbacks of known clock doublers have reduced the advantage of using this clock distribution technique.